Sixth International Conference on Advances in Computing, Control and Networking - ACCN 2017
Author(s) : G. SRIDHAR, M. SUSHAMA, P. SATISH KUMAR
In the past few years the demand for the achievements in development of multilevel inverter topologies has been increasing a lot. Recently presented topologies accomplish higher number output voltage levels with few number of switches, DC voltage sources, and reduced voltage stress across switches, with fewer losses as compared with conventional topologies. Minimization of switches and dc voltage sources reduces complexity, cost size and improves the overall performance. These benefits are proposed in this paper with a new topology of asymmetrical cascaded multilevel inverter. This developed structure provides reduced number of controlled switches, DC sources, as compared with conventional and presented topologies in the literature so far. The proposed asymmetrical topology generates seven voltage levels with eight switches only. Furthermore reduction in voltage stress across the switches can be attained. Phase Opposition Disposition (POD) is adopted for generating switching pulses. The proposed topology is simulated using MATLAB/SIMULINK and results have been validated experimentally.