Conference Proceedings

International Conference on Advances In Engineering And Technology - ICAET 2014

Power and Delay Optimization of 1 Bit Full Adder using MTCMOS Technique

Author(s) : GAURAV SONI, SONAM GOUR, SWATI S.KUMAR

Abstract

In this paper, a 28T full adder using MTCMOS technique design is proposed. Combinational logic has extensive applications in quantum computing, low power VLSI design and optical computing. Reducing power dissipation is one of the most principle subjects in VLSI design today. The subthreshold leakage current becomes a large component of total power dissipation. Low- power design techniques proposed to minimize the active leakage power in nanoscale CMOS very large scale integration (VLSI) systems. In this paper the active power and delay of full adder is analyzed with or without MTCMOS. The power and delay evaluation has been carried out using extensive simulation on the HSPICE circuit simulator. The simulation results are based on 32nm and 45nm Berkeley Predictive Technology Model (BPTM). By using MTCMOS technique in full adder a reduction is observed in the active power is 98.3% in 32nm and 99.1% in 45nm. The reduction in the delay is the 21% for sum output and 25% for carry output in 32nm. In 45nm the reduction in delay is 26% for sum output and 29% for carry output.

Conference Title : International Conference on Advances In Engineering And Technology - ICAET 2014
Conference Date(s) : 24 - 25 May, 2014
Place : RIT, Roorkee, India
No fo Author(s) : 3
DOI : 10.15224/978-1-63248-028-6-02-100
Page(s) : 229 - 232
Electronic ISBN : 978-1-63248-028-6
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