Conference Proceedings

International Conference on Advances In Engineering And Technology - ICAET 2014

A New Technique For Designing Low Power 2-Bit Magnitude Comparator

Author(s) : K. G. SHARMA, TRIPTI SHARMA, VIJAYA SHEKHAWAT   

Abstract

In this paper a new logic technique and hence circuit design has been proposed for the implementation of magnitude comparator. This proposed 2-Bit magnitude comparator is design to improve power consumption as well as on-chip area than its peer design. The proposed 2-Bit magnitude comparator has threshold loss of 13%-20%. This threshold loss is due to PTL (Pass Transistor Logic) logic applied at the input end and at the output end TG (Transmission Gate) logic is used, this is done to reduce the number of transistor. The schematic of 2-Bit magnitude comparator is designed using Tanner EDA Tool version 12.6 at 45nm technology.

Conference Title : International Conference on Advances In Engineering And Technology - ICAET 2014
Conference Date(s) : 24 - 25 May, 2014
Place : RIT, Roorkee, India
No fo Author(s) : 3
DOI : 10.15224/978-1-63248-028-6-02-26
Page(s) : 122 - 126
Electronic ISBN : 978-1-63248-028-6
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