International Conference on Advances in Computer Science and Electronics Engineering - CSEE 2014
Author(s) : AAMIR SHABBIR PARRE , INAYAT-UR-REHMAN , KOKAB WAQAS , MANZOOR ELAHI , TASSAWAR IQBAL
The processor architecture designers face major challenges to improve the processor’s performance. To measure the performance of the processor there are many parameter like performance of cache, TLB, IO operations, bus speed etc. different companies launch series of processors with same base configuration and a little change of variations base on cache size, cache levels, share and separate cache and many other parameters like that. There are many simulators available to measure processor's performance theoretically with several parameters. We simulate some models of Intel Pentium 4 and UltraSPARC II processors and analyze the performance of the processors regarding cache and TLB.