International Conference on Advanced Computing, Communication and Networks - CCN 2011
Author(s) : A.R. KASETWAR, V. G. NASRE
Main building blocks of a SAR-ADC are: sample & hold circuit, comparator, timing and logic control which is mainly SAR logic, DAC (Digital to Analog Converter) in the feedback loop of ADC. For low-power applications designer needs to come up with a compromise among speed and resolution. In this paper the components for SAR ADC are designed in 0.18μm CMOS technology in such a way that the total power is minimized. CMOS has been the dominant technology for VLSI implementation. As VLSI circuits continue to grow and Technologies evolve, the level of integration is increased and higher clock speeds are achieved. Higher clock speeds, increased level of integration and technology scaling are causing unabated increase in power consumption as a result; low power consumption is becoming a critical issue for modern VLSI circuits. For battery operated systems, low power consumption requirements are well understood and followed. Whereas for high performance ICs, reducing the delay has been the main objective, and power containment was secondary. However recent research shows that power containment for high power applications is becoming critical for reliability, transistor performance, and cooling considerations. In this paper we are presenting low power and high speed components of ADC.