International Conference on Advanced Computing, Communication and Networks - CCN 2011
Author(s) : NEELKAMAL, SANDEEP K. ARYA
This paper presents the comparison between CMOS dynamic latch comparators. The circuit has been simulated using SPICE tool with 0.35μm technology, supply voltage of 3 V and 3.3 V respectively. The circuits studied and simulated in this paper are Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch and the Buffered dynamic latch circuit that consists of a basic dynamic latch comparator followed by an inverter buffer stage. The power dissipation of preamplifier latch and buffered latch comparator operating at frequency 160 MHz and 100 MHz are 960.129 μW and 1.132 mW respectively.