Conference Proceedings

International Conference on Advanced Computing, Communication and Networks - CCN 2011

Logical Effort to study and Compare the performance of VLSI Adders

Author(s) : GAURAV DHIMAN, MANOJ KUMAR   , P.K GHOSH, SATYAJIT ANAND

Abstract

CMOS logic gates are basic building blocks for VLSI adder’s circuits. The delay through these gates is related to their sizes and terminal loads. Logical effort is a technique, which gives insight about proper sizing of CMOS logic gates to have the minimum achievable delay. In this paper, we discuss first the technique of logical effort; three common architectures for VLSI adders are sized using logical effort to get the minimum possible delay. Simulated results are used to design fast CMOS circuits. A comparison between delays for these structures is presented according to simulation results in 32 nm standard CMOS process.

Conference Title : International Conference on Advanced Computing, Communication and Networks - CCN 2011
Conference Date(s) : June 2-3, 2011
Place : Hotel Aroma, Chandigarh, India
No fo Author(s) : 4
DOI :
Page(s) : 33 - 38
Electronic ISBN :
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