Conference Proceedings

International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013

Design Of A Delay Block For Low Frequency Switch-capacitor Circuits

Author(s) : ASHISH KUMAR MAL    , BOLLIPELLI SRIKANTH    , RISHI TODANI  , SANDEEP KUMAR DASH   

Abstract

Switch-capacitor (SC) circuits are one of the most popular methods for implementing signal processing blocks such as Integrator, Filters, ADC in CMOS technology. This is primarily due to accurate time constant realization over a wide temperature and process corners. Beside good voltage linearity SC circuits occupies less area than continuous time circuits. Non-overlapping clock (NOC) generator is one of the important blocks of any SC circuit. In standard NOC design, simple CMOS inverters are connected in cascade to implement delay blocks. As technology scales, number of inverter increases affecting the area and power budget of the design. In this work, it is proposed to use two numbers of inverted CMOS inverters and one current starved inverter in cascade as a delay block, to achieve a larger delay for a given area. The proposed delay block is used to realize a ring oscillator and a voltage controlled NOC generator. Simulation result shows that proposed delay block exhibits a larger delay than existing standard delay blocks. As frequency of operation is decreased, the proposed delay block is seen to be more and more advantageous in terms of area and power. The designed NOC generator is used to implement a first order SC integrator. The entire work is carried out using GPDK 90 nm technology with 1.2 V supply.

Conference Title : International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013
Conference Date(s) : April 27-28, 2013
Place : Hotel Vits, Mumbai, India
No fo Author(s) : 4
DOI : 10.15224/978-981-07-6260-5-42
Page(s) : 203 - 208
Electronic ISBN : 978-981-07-6260-5
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