Conference Proceedings

International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013

Decoupling Capacitor Induced Bandwidth and Delay expressions for On-Chip RLC global interconnects

Author(s) : MRIGENDRA KUMAR, NIVEDITA ROUT    , SANDEEP KUMAR DASH   , SANTOSH KU CHHOTRAY   , SUBHAKANTA SWAIN   

Abstract

Continuously scaling down devices is the main goal in deep sub-micron (DSM) technology. Though using DSM technology we are achieving many advantages. But circuit performances are badly affected because of secondary effects like crosstalk noise. According to International Technical Roadmap for Semiconductors(ITRS) 2011 report today’s DSM technology outsmarted Moore’s law to work in a new industrial trend called “More than Moore” (MtM). To accomplish this, it is necessary to analyze the timing behavior of the interconnect. Decoupling capacitor can have significant effect on principal characteristics of an integrated circuit (IC) i.e. speed, cost and power. So by including a decoupling capacitor intentionally can control secondary effects in very deep sub-micron (VDSM) technology. But inserting a decoupling capacitor affects delay and bandwidth of the interconnect. So while inserting decoupling capacitor we have to check for the disturbances in delay and bandwidth. Here in this paper two expressions for calculating delay and bandwidth have derived.

Conference Title : International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013
Conference Date(s) : April 27-28, 2013
Place : Hotel Vits, Mumbai, India
No fo Author(s) : 5
DOI : 10.15224/978-981-07-6260-5-38
Page(s) : 182 - 186
Electronic ISBN : 978-981-07-6260-5
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