International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013
Author(s) : A. H. KARODE , ASHISH S. BHAISARE , S. R. SURALKAR
The main objective of this paper is to describe an efficient hardware-based concept of a digital video WM system which features low power consumption, efficient and low cost implementation, high processing speed, reliability and invisible, semi-fragile watermarking in compressed video streams. The presented WM system can be integrated with video compressor unit and it achieves performance that matches complex software algorithms within a simple efficient hardware implementation. The system also features minimum video quality degradation and can withstand certain potential attacks i.e. cover-up attack, cropping, segment removal on video sequences. The proposed WM system is implemented using Verilog hardware description language (HDL) synthesized into a field programming gate array (FPGA) and then experimented using a custom versatile breadboard for performance evaluation is describe through various research papers which give a vital review related to digital video watermarking system for video authentication.