Conference Proceedings

International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013

Performance Improvement of Diode Clamped Multilevel Inverter Using Carrier Based PWM Scheme and Balancing Circuit

Author(s) : LOHIT RAVINDRA CHAUDHARY   , MADHUKAR M. WAWARE   

Abstract

Multilevel inverter (MLI) has attracted huge interest in high power and medium voltage application. MLI provides higher power quality at the ac side, can operate at higher ac voltage levels and minimize or even eliminate the interface transformer. It reduces the required voltage rating of the power semiconductor devices. It enables to work at lower switching frequency, so it produces less number of harmonics, lower switching losses and lowerelectromagnetic interference (EMI). Diode clamped inverter (DCI) is one of the most popular topology of the MLI, has achieved huge demand in industrial application and renewable energy system.Among the problem concerning DCI, balancing of the voltages in the dc – link capacitors of diode clamped multilevel inverter with more than three levels is a great challenge. This paper presents carrier based pulse width modulation scheme for five-level diode clamped inverter where the voltage across each capacitor in the dc – link of five-level DCI is maintained constant using a balancing circuit. Simulation results of a five-level DCI are given to validate the performance of proposed scheme.

Conference Title : International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2013
Conference Date(s) : April 27-28, 2013
Place : Hotel Vits, Mumbai, India
No fo Author(s) : 2
DOI : 10.15224/978-981-07-6260-5-07
Page(s) : 26 - 30
Electronic ISBN : 978-981-07-6260-5
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