First International Conference on Advances in Computer, Electronics and Electrical Engineering - CEEE 2012
Author(s) : M.SARASWATHI
In this paper the design of 128/64 point Fast Fourier transform processor (FFT Processor) is proposed to support future generation Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO OFDM) based IEEE 802.11n wireless local area network base band processor. The pipelined mixed radix delay feedback (MRMDF) FFT architecture is proposed to provide a higher throughput rate combining the characteristics of both Single path Delay Feedback (SDF) which is used to reduce memory size and Multipath Delay Commutator (MDF) by using the multidata-path scheme. That is higher throughput rate can be provided by using four parallel data path. The proposed processor not only supports the operation of FFT in 128 point and 64 point but can also provide different throughput rates for 1-4 simultaneous data sequence to meet IEEE 802.11n requirements. Further, less complexity is needed in this deign compared with traditional four parallel approach. The hardware cost of memory and complex multipliers are less using this proposed FFT/IFFT processor, since this paper is done by using delay feedback and data scheduling approach. The higher order radix FFT algorithm reduces the number of complex multiplication. The proposed FFT/IFFT processor requires minimum memory since feedback approach is used for reordering the input data and the immediate results of each module. The mixed radix FFT algorithm is used to save power consumption and is measured as 296.96 mW and of Minimum period within 6.204ns (Maximum Frequency: 161.188MHZ) This paper is VLSI based and the language used is VHDL. The software used for simulation of this paper is XILINX 8.2.